With the proliferation of data-intensive applications, such as sound, image and video processing, the memory subsystem has become an important focus of electronic system design. More than three-quarters of a data-intensive system can be made up of storage components, making the memory subsystem the most crucial part of the design of an integrated circuit. Most of these systems need to be high-speed due to the large amounts of data involved and must be designed carefully to avoid a solution that is larger than expected.
The design of an integrated circuit no longer begins with a circuit diagram. Instead, it begins with a software program that describes the behavior or functionality of a circuit. This software program is a source code description that defines an algorithm to be performed with limited implementation details. Designers direct behavioral synthesis tools to convert the source code description into a register transfer level (RTL) description. The RTL description is used to ultimately generate a netlist that includes a list of components in the circuit and the interconnections between the components. This netlist is used to create the physical integrated circuit.
Arrays provide a powerful and convenient method for modeling the behavior of memories in source code descriptions. That is, behavioral descriptions are used to manipulate groups of data in an abstract manner using arrays. These arrays are, under the control of the designer, packed to memory. Behavioral synthesis tools automatically construct the logic to control the memory, freeing the designer to explore architectures using different memories with different characteristics (e.g., synchronous versus asynchronous, single port versus dual port), and make intelligent decisions about an appropriate implementation for a design.
To pack arrays to a memory, the designer must specifically assign the variables representing the arrays to a memory in source code and specify the type of memory and other memory parameters. This is accomplished using a set of attributes or directives. For example, Synopsis® tools use a “pragma” statement.
After the designer designates the details of memory allocation in the source code description (using pragma statements or other directives), the designer runs the source code description through the synthesis tool. The synthesis tool generates a report that the designer can use to analyze the performance of the circuit. For example, the user can examine the speed and area of the circuit to determine whether the current memory allocation is acceptable. If the memory allocation is not acceptable, the designer must return to an editor, re-edit the source code description to change the details of memory allocation, and run the source code description through the synthesis tool again. Such a technique for modifying the memory allocation is time consuming and inefficient and gives the designer only a limited amount of options for designating how memory will be allocated.
It is desirable, therefore, to provide a method and synthesis tool that allows a designer to modify memory resources more quickly and simply as well as provide the designer with more advanced options for specifying how arrays will be packed to memory.